Semiconductor IP: Mask Work and Layout-Design Planner
Where IP meets regulation in fast-moving technology: open-source licensing, AI governance across the EU, India and the US, chip layout-design protection, and climate-tech classification.
Key developmentsUpdated Oct 2026 · 2 items
- Budget 2026 launches India Semiconductor Mission 2.0
Support widens from fabs to equipment, materials and full-stack Indian chip IP.
Source: Business Today ↗ - Vikram 3201 unveiled at Semicon India 2025
A 32-bit processor developed by the Semiconductor Laboratory, presented as India's first home-grown chip.
Source: The Register ↗
Example tape-out loaded.
| Route | Deadline / term | Status |
|---|---|---|
| EP patent: novelty lost by the disclosure unless filed earlierEPC Art. 54 — no general grace period | 18 Jun 2026 | Passed |
| US patent: file within the inventor-disclosure grace period35 U.S.C. §102(b)(1)(A) | 18 Jun 2027 | Upcoming |
| India patent: only if the disclosure falls within ss.29–34e.g. s.31 exhibitions or learned-society papers; ordinary publication is not covered | 18 Jun 2027 | Upcoming |
| India layout-design: file before the 2-year barSICLD Act — not registrable if commercially exploited more than 2 years before filing | 03 Nov 2027 | Upcoming |
| US mask work: register with the Copyright Office17 U.S.C. §908(a) — protection ends if not registered within 2 years | 03 Nov 2027 | Upcoming |
| Layout-design term ends (India and US)10 years; India counts from filing or first exploitation, US from registration or first exploitation, whichever is earlier | 03 Nov 2035 | Upcoming |
| Process know-how: keep as a trade secretNo registration. Access controls, NDAs and marking; India relies on contract and equity, the US on the DTSA | — | Ongoing |
India: Semiconductor Integrated Circuits Layout-Design Act, 2000. US: Semiconductor Chip Protection Act, 17 U.S.C. §§901–914. Patent grace periods differ: the US allows one year for the inventor's own disclosure, India allows only narrow exceptions under ss.29–34, and the EPC has no general grace period. Verify before relying.
Desk reference · Layout-design protection
| Point | India | United States | European Union |
|---|---|---|---|
| Statute | SICLD Act, 2000 | Semiconductor Chip Protection Act, 1984 | Directive 87/54/EEC, national laws |
| Registration | Required; Layout-Design Registry | Required within 2 years of first commercial exploitation | Varies by member state |
| Bar | Not registrable if commercially exploited more than 2 years before filing | Protection lost if not registered in time | National rules apply |
| Term | 10 years | 10 years | 10 years |
| Originality | Original, distinctive, not commonly known | Original, not staple or commonplace | Own intellectual creation, not commonplace |
| Reverse engineering | Permitted for analysis and teaching | Permitted, including to build an original chip | Permitted for analysis and teaching |
Tools
Design Data Export Screen
A checklist for sharing RTL, GDSII and EDA tooling across borders under export-control rules.
Foundry Engagement Checklist
NDA, PDK licence, IP ownership and yield-data terms for a first tape-out.
Semiconductor Patent Landscape Starter
CPC-based query sets for packaging, power devices, memory and lithography.
Questions practitioners ask.
Short answers to the questions US patent attorneys and in-house teams ask most about India, with the rule behind each one. Reviewed October 2026.
How long does chip layout-design protection last, and when must you register?
Ten years in both India and the US. In the US, a mask work must be registered within two years of first commercial exploitation or protection ends. In India, a layout design exploited commercially for more than two years before filing cannot be registered.
More tools.
Live toolIndia Patent Deadline Calculator
Calculate Indian patent deadlines under the 2024 Rules: 31-month national phase, Form 18, Form 3, FER response, Form 27 and renewals. Indian forms mapped to US practice.
Live toolOpen-Source Licence Compatibility Checker
Check GPL, LGPL, AGPL, MPL, Apache-2.0 and MIT components against your outbound licence for distributed, SaaS and internal products. EU Cyber Resilience Act dates included.
Live toolAI Obligation Mapper
Map AI obligations by role and market: EU AI Act dates after the 2026 Omnibus, India IT Rules synthetic-content labelling, DPDP Act and the amended Colorado AI Act.
Live toolClimate-Tech Classifier
Suggest CPC Y02 and Y04S climate-tech tags from an abstract for green patent landscapes and portfolio reporting, with India carbon market developments.
Live toolIndia IP Assignment Check
Why work-made-for-hire fails for Indian contractors. Check assignments against Copyright Act s.19 defaults, Patents Act s.68, Section 39 foreign filing and stamp duty.
Live toolConsultation Comment Builder
Track Indian IP, AI and data policy developments with sources, and draft clause-by-clause comments for Indian government consultations.
Live · FlagshipFFL Planner
Sequence foreign filing licences and first filings across jurisdictions, including India s.39 and US 35 U.S.C. 184 permissions.